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Abstract: Innovative SOI material and device

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Abstract: This work aims to demonstrate the experimental results of SHE in fully depleted (FD) Ω-gate SOI Nanowire MOSFETs obtained using the gate resistance thermometry technique in a wide temperature range from 300K down to 4.2K.

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Abstract: This paper presents the results of substrate-loss reductions at RF and mm-wave frequencies achieved in 28 nm FD-SOI by running the process for the first time on wafers with high bulk resistivities. Parasitic conduction at the interface is removed using the PN-junction passivation technique. 10 wafers were run with splits in the PN implant doses and energies, highlighting the good practices to be performed to achieved an optimally passivated interface. This is quantified through the on-wafer measurements on CPW lines on all substrates. Overall, this work demonstrates excellent RF substrate loss reductions in 28 nm FD-SOI using HR substrates, that is even further enhanced using the optimized PN passivation process.

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Abstract: The requirements for electronic devices to withstand high temperatures have expanded, especially in sectors like oil exploration, aeronautics and automotive. Silicon-On-Insulator (SOI) MOSFETs are preferred for their fast switching and low leakage, showing superior high-temperature stability. However, they face self heating effect (SHE) due to poor heat dissipation through the buried oxide (BOX) [1]. SiC, with excellent thermal conductivity, is a better alternative to replace the BOX [2]. Using Si-On-SiC (SOSiC) substrates greatly improves the heat dissipation, reducing performance degradation due to SHE [3]. In this paper, we fabricated prototype SOSiC wafers by hydrophobic surface activation bonding (SAB) and analyzed the SHE of SOI and SOSiC MOSFETs using the calibrated TCAD simulations (Fig. 1). Their electrothermal properties, temperature rise, and thermal resistance are addressed. Furthermore, we investigated the heat dissipation paths of SOI and SOSiC MOSFETs, and elucidated the impact of the geometrical configuration of the devices on the relationship between temperature rise, thermal resistance, and dissipation pathways Fig. 2 shows that SOI MOSFETs suffer more serious on-state current degradation than SOSiC. At room temperature, the hot-spots are 347 K for SOI and 310 K for SOSiC, located near the LDD boundary due to uneven heat distribution (Fig. 3). The temperature rise and thermal resistance of the SOI MOSFETs are 3.9 and 4.1 times higher than those of SOSiC MOSFETs, which are more efficient in reducing junction temperature at same power levels. The comparison of the heat flux ratios across thermal contacts shows that SOI MOSFETs primarily dissipate heat through the drain and source (33.7% and 32.9%), while the substrate is the main heat path for SOSiC (85.6%), see Fig. 4 and 5. As the epilayer thickness increases from 0.1 μm to 0.3 μm, the temperature rises in SOI by 52.4% despite the thermal resistance decreases by 1.8% (Fig. 6), which indicates that the increased current in thicker layers has a greater effect on SHE than the reduction in thermal resistance. For SOSiC, the temperature rise also increases for thicker layers but is limited to 15 K (Fig. 6). Meanwhile, heat dissipation through the source, drain, gate, and substrate indicates a correlation between dissipation paths and epilayer thickness. (Fig. 6).

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Abstract: In this paper, the impact of thermal cross-coupling between two side-by-side FD-SOI MOSFETs is studied at both room (295 K) and liquid nitrogen (77 K) temperatures. Through DC measurements, it is demonstrated that the degradation of electrical parameters caused by the operation (i.e. heating) of the neighbor can be up to 50 % more important at 77 K than at 295 K.

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Abstract: The demand for low temperature circuits in various applications, including space electronics, data center power reduction, and quantum computing, necessitates the re-design and verification of the Room Temperature (RT) circuits designed for operation at cryogenic temperatures. Threshold voltage (Vth) increase with the temperature reduction is a major challenge, which can significantly affect circuit operation. This paper investigates the impact of back biasing and threshold voltage engineering on the performance of FDSOI based circuits at cryogenic temperatures. Additionally, we explore supply voltage (VDD) reduction for power budgets and propose Vth engineering as a solution to optimize power/speed trade-offs.

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Abstract: We discuss the endurance and retention characteristics of a compact, one-transistor capacitorless cryogenic memory based on impact ionization in bulk CMOS devices. The memory has a retention time on order of minutes at T < 10 K, a high memory window of ~10e7, and does not degrade over 10e9 cycles. This type of device could find application as a local memory for quantum sensing and computing applications.

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Abstract: This work details transport parameters of n-type 7-level stacked nanosheet GAA MOSFETs. The contributions of horizontal and sidewalls to mobility and degradation factors are analyzed separately in NS with several channel lengths. The analysis is performed using experimental data of devices with different channel lengths and nanosheet width from 15 nm to 55 nm.

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Abstract: Nanosheet Field-Effect Transistors (NSFETs) have been introduced in the 3nm CMOS technology due to advantages over the FinFET technology. In this paper, using our in-house NanoElectronics Simulation Software (NESS), we explore the mobility and the intrinsic performance of NSFETs for different channel orientations. The effective masses for different cross sections and channel orientations are extracted from the first principal simulations. The mobility and the intrinsic performance will be evaluated using the effective mass based on the non-equilibrium Green’s function (NEGF) and Kubo-Greenwood simulation engines of NESS. The proposed work provides insight into the optimised parameters for NSFET configurations suitable for 3nm and further technology nodes.

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Abstract: This preliminary study aims to report a possible new MOS device with a stack of magnetic gates, for example in 28 nm FD-SOI UTBB technology. This study focuses on a proposed stacking in a MOS gate through 3D HFSS numerical simulations to evaluate the magnetic field gradient under and around the MOS device. Typically, the polycrystalline gate is replaced by a magnetic material with metallic behavior to also enable conventional electrostatic MOS control. The dimensions meet 28nm design requirements and Co or Ni magnetic materials are candidates for process integration. In addition, other materials should be selected based on the magnetic specifications and metal work function. Applications could be with an internal or external magnetic field environment for quantum or sensor applications. 3D magnetic simulations are carried out with the HFSS tool.

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Abstract: In LWIR band, pn diodes represent an attractive solution for thermometers in microbolometers. In this paper, epitaxial short p+ pn+ diodes were studied at 303-353 K. A TCC at 4.6-6.2 %/K and a noise dominated by ficker noise were measured. Finally, a thermal resolution between 2.10^(-3) and 5.10^(-2) K was obtained at 303 K. It offers promising performances for future microbolometers.

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Abstract: This study presents a thorough investigation of the Hf-Zr (Hf0.5Zr0.5O2 - HZO) layer and the subsequent steps towards its integration into 3D gate-all-around devices, currently targeted for the next technology nodes in logic architecture. MIS devices are presented, with a 10nm HZO layer, that display through GIXRD the successful crystallization of HZO with annealing temperatures starting as low as 400°C. The ferroelectricity and thus the orthorhombic crystalline phase of HZO is verified through pulsed electrical measurements which exhibit a robust (P-E) hysteresis loop. Integration on vertical nanostructured channels has been successfully demonstrated with a perfect conformity of the layer. In a 3D nanoscale configuration, identifying the proper ferroelectric phase with classical approaches (such as GIXRD) used in planar structures is not feasible. So, we developed a novel approach that couples 4DSTEM imaging and python based data processing to perform a full mapping of the grains and crystalline phases of our HZO layer. Furthermore, we investigate the challenges related to integrating the HZO layer into 3D nanostructures, particularly selective and anisotropic etching steps, to maintain the integrity of the HZO layer. This ensures the removal of unwanted layers from our nanostructures while preserving the surrounding HZO layer, facilitating the subsequent formation of alloy contacts. Additionally, considering the opportunities and possible limitations of fabrication parameters, we explore different process routes in parallel (S/D contact first/last) for the 3D integration of HZO in gate all-around FeFETs , discussing the pros and cons of each configuration (metallurgy stability of the contacts, doping segregation at the interfaces etc).

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Abstract: The introduction of GeSn as a channel material, with its modulated band structure and high carrier mobilities for both electrons and especially holes, is promising for optoelectronics and Beyond- CMOS technologies with high on-state conductance as well as low power cryogenic applications. Therefore, forming high-quality contacts to the GeSn is of utmost importance. In this regard, we investigate the Al contact formation to nanosheets composed of thin GeSn layers with Sn concentrations from 0.5% to 4%. The nanosheets are patterned from vertical Si/Ge1-xSnx/Si heterostructures, grown on SOI substrates by molecular beam epitaxy (MBE) at ultra-low temperatures of 175°C. Utilizing a thermally induced exchange reaction between Al and Si/GeSn, monolithic metal-semiconductor-metal lateral heterostructures with abrupt Al-GeSn junctions are formed. Implemented in field-effect transistors, the electrical transport is investigated, revealing linear IV-characteristics, suggesting highly transparent quasi-ohmic contacts. The transfer characteristics show a very dominant p-type conduction, which can be attributed to strong Fermi level pinning to the valance band and potentially also to hole-gas formation between the 4 nm thin GeSn layer sandwiched vertically between two Si layers. Temperature-dependent measurements indicate that at cryogenic temperatures, the GeSn channel can be sufficiently depleted due to fewer thermally excited states at VG > 0. This results in a drain current modulation over three orders of magnitude, while the on-currents remain mostly temperature-independent, making the system especially interesting for cryo-CMOS applications. The comparison of nanosheets with different stoichiometries shows that an increased Sn content enhances conductivity, over 20x higher vs. a control sample with a pure Ge layer in agreement with an accumulation channel. However, the off-state is given by depletion implying a VG dependent overall gate capacitance accompanied with degraded Ion/Ioff ratios and subthreshold slopes. To decouple the influence of the carrier injection barrier and the channel conduction, a multi-gate structure, featuring a junction gate (JG) atop the Al-GeSn interfaces and a channel gate (CG) in the middle of the GeSn channel, is investigated. Thereby, it was found that keeping VJG at -5 V and sweeping VCG, the on-state resistance can be improved by a factor of ~40.