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EuroSOI-ULIS 2024 timetable


EuroSOI-ULIS 2024 poster session




08:30 - 09:00
Registration learn more
Room: Conference Secretariat, Oasis Hotel Apartments
09:00 - 09:20
Opening learn more
Opening Session
Panagiotis Dimitrakis
Vasilios Ioannou
Pascal Normand
Christos Tsamis
09:20 - 10:45
Session 1 learn more
Session 1

From 3D devices to 3D stacking, next challenges and perspectives

Presenter: Thomas Ernst

Enhanced Threshold Voltage Tuning in SOI MOSFET with Ferro-BOX
Presenter: Sorin Cristoloveanu (SOITEC)
Authors: Sorin Cristoloveanu
Abstract: Innovative SOI material and device
Experimental Extraction of Self-Heating in SOI Nanowire MOSFETs at Cryogenic Temperatures
Presenter: Marcelo Pavanello (Centro Universitario FEI)
Authors: Flavio Bergamaschi, Jefferson Matos, Jaime Rodrigues, Giovanni Matos, Sylvain Barraud, Mikaël Cassé, Olivier Faynot, Marcelo Pavanello
Abstract: This work aims to demonstrate the experimental results of SHE in fully depleted (FD) Ω-gate SOI Nanowire MOSFETs obtained using the gate resistance thermometry technique in a wide temperature range from 300K down to 4.2K.
11:00 - 13:00
Session 2 learn more
Session 2
Low-Loss Silicon Substrates with PN Passivation in 28 nm FD-SOI
Presenter: Martin Rack (Université catholique de Louvain)
Authors: Martin Rack, Massinissa Nabet, Maxime Moulin, Youssef Bendou, Martin Vanbrabant, Quentin Courte, Sébastien Cremer, Andreia Cathelin, Dimitri Lederer, Jean-Pierre Raskin
Abstract: This paper presents the results of substrate-loss reductions at RF and mm-wave frequencies achieved in 28 nm FD-SOI by running the process for the first time on wafers with high bulk resistivities. Parasitic conduction at the interface is removed using the PN-junction passivation technique. 10 wafers were run with splits in the PN implant doses and energies, highlighting the good practices to be performed to achieved an optimally passivated interface. This is quantified through the on-wafer measurements on CPW lines on all substrates. Overall, this work demonstrates excellent RF substrate loss reductions in 28 nm FD-SOI using HR substrates, that is even further enhanced using the optimized PN passivation process.
Comparison of Self Heating Effect between SOI and SOSiC MOSFETs
Presenter: Huiping Zhu (Institute of Microelectronics, Chinese Academy of Sciences)
Authors: Jiamin Li, Fanyu liu, Bo Li, Huiping Zhu, Jiangjiang Li, Xiaogang Yao, Baogang Sun, Yang Huang, Jing Wan, Yong Xu, Sorin Cristoloveanu
Abstract: The requirements for electronic devices to withstand high temperatures have expanded, especially in sectors like oil exploration, aeronautics and automotive. Silicon-On-Insulator (SOI) MOSFETs are preferred for their fast switching and low leakage, showing superior high-temperature stability. However, they face self heating effect (SHE) due to poor heat dissipation through the buried oxide (BOX) [1]. SiC, with excellent thermal conductivity, is a better alternative to replace the BOX [2]. Using Si-On-SiC (SOSiC) substrates greatly improves the heat dissipation, reducing performance degradation due to SHE [3]. In this paper, we fabricated prototype SOSiC wafers by hydrophobic surface activation bonding (SAB) and analyzed the SHE of SOI and SOSiC MOSFETs using the calibrated TCAD simulations (Fig. 1). Their electrothermal properties, temperature rise, and thermal resistance are addressed. Furthermore, we investigated the heat dissipation paths of SOI and SOSiC MOSFETs, and elucidated the impact of the geometrical configuration of the devices on the relationship between temperature rise, thermal resistance, and dissipation pathways Fig. 2 shows that SOI MOSFETs suffer more serious on-state current degradation than SOSiC. At room temperature, the hot-spots are 347 K for SOI and 310 K for SOSiC, located near the LDD boundary due to uneven heat distribution (Fig. 3). The temperature rise and thermal resistance of the SOI MOSFETs are 3.9 and 4.1 times higher than those of SOSiC MOSFETs, which are more efficient in reducing junction temperature at same power levels. The comparison of the heat flux ratios across thermal contacts shows that SOI MOSFETs primarily dissipate heat through the drain and source (33.7% and 32.9%), while the substrate is the main heat path for SOSiC (85.6%), see Fig. 4 and 5. As the epilayer thickness increases from 0.1 μm to 0.3 μm, the temperature rises in SOI by 52.4% despite the thermal resistance decreases by 1.8% (Fig. 6), which indicates that the increased current in thicker layers has a greater effect on SHE than the reduction in thermal resistance. For SOSiC, the temperature rise also increases for thicker layers but is limited to 15 K (Fig. 6). Meanwhile, heat dissipation through the source, drain, gate, and substrate indicates a correlation between dissipation paths and epilayer thickness. (Fig. 6).
Thermal-coupling characterization of FD-SOI FETs at cryogenic temperatures
Presenter: Martin Vanbrabant (Université catholique de Louvain)
Authors: Martin Vanbrabant, Jean-Pierre Raskin, Valeriya Kilchytska
Abstract: In this paper, the impact of thermal cross-coupling between two side-by-side FD-SOI MOSFETs is studied at both room (295 K) and liquid nitrogen (77 K) temperatures. Through DC measurements, it is demonstrated that the degradation of electrical parameters caused by the operation (i.e. heating) of the neighbor can be up to 50 % more important at 77 K than at 295 K.
Enhancing Cryogenic Performance of FDSOI Logic Circuits Using Back Biasing and Threshold Voltage Engineering
Presenter: Tapas Dutta (Semiwise Ltd.)
Authors: Djamel Bensouiah, Fikru Adamu-Lema, Asen Asenov, Tapas Dutta
Abstract: The demand for low temperature circuits in various applications, including space electronics, data center power reduction, and quantum computing, necessitates the re-design and verification of the Room Temperature (RT) circuits designed for operation at cryogenic temperatures. Threshold voltage (Vth) increase with the temperature reduction is a major challenge, which can significantly affect circuit operation. This paper investigates the impact of back biasing and threshold voltage engineering on the performance of FDSOI based circuits at cryogenic temperatures. Additionally, we explore supply voltage (VDD) reduction for power budgets and propose Vth engineering as a solution to optimize power/speed trade-offs.
High-Endurance Bulk CMOS One-Transistor Cryo-Memory
Presenter: Curt Richter (National Institute of Standards and Technology)
Authors: Curt Richter, Alexander Zaslavsky
Abstract: We discuss the endurance and retention characteristics of a compact, one-transistor capacitorless cryogenic memory based on impact ionization in bulk CMOS devices. The memory has a retention time on order of minutes at T < 10 K, a high memory window of ~10e7, and does not degrade over 10e9 cycles. This type of device could find application as a local memory for quantum sensing and computing applications.
Analysis of Electron Mobility in 7-Level Stacked Nanosheet GAA nMOSFETs
Presenter: Michelly de Souza (FEI)
Authors: Michelly de Souza, Jaime Rodrigues, Lucas Mota Barbosa da Silva, Flavio Bergamaschi, Mikaël Cassé, Sylvain Barraud, Olivier Faynot, Marcelo Pavanello
Abstract: This work details transport parameters of n-type 7-level stacked nanosheet GAA MOSFETs. The contributions of horizontal and sidewalls to mobility and degradation factors are analyzed separately in NS with several channel lengths. The analysis is performed using experimental data of devices with different channel lengths and nanosheet width from 15 nm to 55 nm.
14:15 - 16:15
Poster Session learn more
Poster Session
16:30 - 20:00
Session 3 learn more
Session 3

Unconventional Computing with Novel Materials: Promises and Challenges

Presenter: Georgios Ch. Sirakoulis

Mobility and intrinsic performance of silicon-based Nanosheet FETs at 3nm CMOS and beyond
Presenter: Ankit Dixit (University of Glasgow, UK )
Authors: Vihar Georgiev, Naveen Kumar, Ali Rezaei, Nikolas Xeni, Ismail Topaloglu, Tapas Dutta , Preslav Aleksandrov, Asen Asenov, Ankit Dixit
Abstract: Nanosheet Field-Effect Transistors (NSFETs) have been introduced in the 3nm CMOS technology due to advantages over the FinFET technology. In this paper, using our in-house NanoElectronics Simulation Software (NESS), we explore the mobility and the intrinsic performance of NSFETs for different channel orientations. The effective masses for different cross sections and channel orientations are extracted from the first principal simulations. The mobility and the intrinsic performance will be evaluated using the effective mass based on the non-equilibrium Green’s function (NEGF) and Kubo-Greenwood simulation engines of NESS. The proposed work provides insight into the optimised parameters for NSFET configurations suitable for 3nm and further technology nodes.
Preliminary numerical study on magnet gate in MOS FD-SOI for quantum and sensor applications
Presenter: Philippe Galy (STMicroelectronics)
Authors: Philippe Galy, Franck Sabatier, Fabien Ndagijimana, Dominique Drouin
Abstract: This preliminary study aims to report a possible new MOS device with a stack of magnetic gates, for example in 28 nm FD-SOI UTBB technology. This study focuses on a proposed stacking in a MOS gate through 3D HFSS numerical simulations to evaluate the magnetic field gradient under and around the MOS device. Typically, the polycrystalline gate is replaced by a magnetic material with metallic behavior to also enable conventional electrostatic MOS control. The dimensions meet 28nm design requirements and Co or Ni magnetic materials are candidates for process integration. In addition, other materials should be selected based on the magnetic specifications and metal work function. Applications could be with an internal or external magnetic field environment for quantum or sensor applications. 3D magnetic simulations are carried out with the HFSS tool.
Epitaxial p+pn+ vertical short diodes for microbolometers
Presenter: Romain Kubica (CEA-Leti / DOPT)
Authors: Romain Kubica, Antoine Albouy, Mélanie Le Cocq, Frédéric Gonzatti, Francis Balestra, Patrick Leduc
Abstract: In LWIR band, pn diodes represent an attractive solution for thermometers in microbolometers. In this paper, epitaxial short p+ pn+ diodes were studied at 303-353 K. A TCC at 4.6-6.2 %/K and a noise dominated by ficker noise were measured. Finally, a thermal resolution between 2.10^(-3) and 5.10^(-2) K was obtained at 303 K. It offers promising performances for future microbolometers.
Engineering Thin HZO Ferroelectric Layers: From Material Study to 3D Integration for Vertical Gate-All-Around FeFETs
Presenter: Konstantinos Moustakas (LAAS - CNRS)
Authors: Konstantinos Moustakas, Leonardo Cancellara, Niccolo Pezzato, Aurélie Lecestre, Thomas Mikolaijk, Jens Trommer, Guilhem Larrieu
Abstract: This study presents a thorough investigation of the Hf-Zr (Hf0.5Zr0.5O2 - HZO) layer and the subsequent steps towards its integration into 3D gate-all-around devices, currently targeted for the next technology nodes in logic architecture. MIS devices are presented, with a 10nm HZO layer, that display through GIXRD the successful crystallization of HZO with annealing temperatures starting as low as 400°C. The ferroelectricity and thus the orthorhombic crystalline phase of HZO is verified through pulsed electrical measurements which exhibit a robust (P-E) hysteresis loop. Integration on vertical nanostructured channels has been successfully demonstrated with a perfect conformity of the layer. In a 3D nanoscale configuration, identifying the proper ferroelectric phase with classical approaches (such as GIXRD) used in planar structures is not feasible. So, we developed a novel approach that couples 4DSTEM imaging and python based data processing to perform a full mapping of the grains and crystalline phases of our HZO layer. Furthermore, we investigate the challenges related to integrating the HZO layer into 3D nanostructures, particularly selective and anisotropic etching steps, to maintain the integrity of the HZO layer. This ensures the removal of unwanted layers from our nanostructures while preserving the surrounding HZO layer, facilitating the subsequent formation of alloy contacts. Additionally, considering the opportunities and possible limitations of fabrication parameters, we explore different process routes in parallel (S/D contact first/last) for the 3D integration of HZO in gate all-around FeFETs , discussing the pros and cons of each configuration (metallurgy stability of the contacts, doping segregation at the interfaces etc).
Si/Ge1-xSnx/Si transistors with highly transparent Al contacts
Presenter: Lukas Wind (Institute of Solid-State Electronics, TU Wien, 1040 Vienna, Austria)
Authors: Lukas Wind, Stefan Preiß, Daniele Nazzari, Martina Bažíková, Johannes Aberl, Enrique Prado-Navarrete, Moritz Brehm, Lilian Vogl, Masiar Sistani, Walter M. Weber
Abstract: The introduction of GeSn as a channel material, with its modulated band structure and high carrier mobilities for both electrons and especially holes, is promising for optoelectronics and Beyond- CMOS technologies with high on-state conductance as well as low power cryogenic applications. Therefore, forming high-quality contacts to the GeSn is of utmost importance. In this regard, we investigate the Al contact formation to nanosheets composed of thin GeSn layers with Sn concentrations from 0.5% to 4%. The nanosheets are patterned from vertical Si/Ge1-xSnx/Si heterostructures, grown on SOI substrates by molecular beam epitaxy (MBE) at ultra-low temperatures of 175°C. Utilizing a thermally induced exchange reaction between Al and Si/GeSn, monolithic metal-semiconductor-metal lateral heterostructures with abrupt Al-GeSn junctions are formed. Implemented in field-effect transistors, the electrical transport is investigated, revealing linear IV-characteristics, suggesting highly transparent quasi-ohmic contacts. The transfer characteristics show a very dominant p-type conduction, which can be attributed to strong Fermi level pinning to the valance band and potentially also to hole-gas formation between the 4 nm thin GeSn layer sandwiched vertically between two Si layers. Temperature-dependent measurements indicate that at cryogenic temperatures, the GeSn channel can be sufficiently depleted due to fewer thermally excited states at VG > 0. This results in a drain current modulation over three orders of magnitude, while the on-currents remain mostly temperature-independent, making the system especially interesting for cryo-CMOS applications. The comparison of nanosheets with different stoichiometries shows that an increased Sn content enhances conductivity, over 20x higher vs. a control sample with a pure Ge layer in agreement with an accumulation channel. However, the off-state is given by depletion implying a VG dependent overall gate capacitance accompanied with degraded Ion/Ioff ratios and subthreshold slopes. To decouple the influence of the carrier injection barrier and the channel conduction, a multi-gate structure, featuring a junction gate (JG) atop the Al-GeSn interfaces and a channel gate (CG) in the middle of the GeSn channel, is investigated. Thereby, it was found that keeping VJG at -5 V and sweeping VCG, the on-state resistance can be improved by a factor of ~40.
08:30 - 09:00
Registration learn more
09:00 - 11:05
Session 4 learn more
Session 4
Organic neuromorphic electronics for emulating and interfacing biological systems
Presenter: Paschalis Gkoupidenis (Max Planck Institute for Polymer Research)
Authors: Paschalis Gkoupidenis
Temperature-Dependent Electronic Transport in Reconfigurable Transistors based on Ge on SOI and Strained SOI Platforms
Presenter: Andreas Fuchsberger (Institute of Solid-State Electronics, Technische Universität Wien, Vienna, Austria)
Authors: Andreas Fuchsberger, Lukas Wind, Daniele Nazzari, Johannes Aberl, Enrique Prado-Navarrete, Moritz Brehm, Lilian Vogl, Peter Schweizer, Masiar Sistani, Walter M. Weber
Abstract: Nanoscale Ge has been identified as a promising channel material to enable reduction of power consumption and enhancement of switching speed of reconfigurable field-effect transistors (RFETs). Such multi-gate transistors allow the run-time switching between n- and p-type operation in a single device. Here, we bypass fabrication and stability issues of Ge on insulator (GeOI) RFETs, first by growing Ge on top of a <110> SOI substrate by low-temperature molecular-beam epitaxy, constituting our Ge on SOI (GeSOI) platform. To obtain thicker and more relaxed Ge layers, a strained-Si on insulator (s-SOI) platform was established. Importantly, in this work, the specific characteristics and benefits of the proposed Ge-based RFETs are discussed by a systematic temperature-dependent investigation of the electrical gating-related charge carrier transport to extract the electronic transport regimes and activation energies.
Resistive Switching phenomenon in FD-SOI Ω-Gate FETs: transistor performance recovery and back gate bias influence
Presenter: Carlos Andrés Valdivieso León (Universitat Autonoma de Barcelona)
Authors: Carlos Andrés Valdivieso León, Rosana Rodríguez, Albert Crespo-Yepes, Javier Martín-Martínez, Montserrat Nafria
Abstract: Resistive Switching (RS) phenomenon has acquired a lot of interest in the scientific community because its potential use in many applications such as memory, logic, security, neuromorphic systems, etc. Devices where RS is observed are usually named as memristors and, after a forming process, RS provokes a reversible change in the device dielectric conductance between a high and a low resistance state (after a set process) and vice versa (reset process) when a correct bias is applied. Usually, memristors are two-terminal capacitive structures, but RS has also been observed previously in FD-SOI quasi-planar transistors. The RS observation in transistors opens the possibility of using the device in a versatile mode as transistor or memristor, as necessary. In this work, for the first time, partial recovery of the transistor characteristics during RS is investigated in N-type FDSOI Ω-gate nanowire FETs with high-k dielectric. On the other hand, other works have observed the influence of the back gate voltage (VB) in the main parameters of Ω -gate nanowires transistors, but none of them have analyzed the effect of this biasing on RS, so that, in this work it is also investigated the influence of VB on RS
Preliminary results on industrial 28nm FD-SOI phase change memory at cryogenic temperature
Presenter: Philippe Galy (STmicroelectronics)
Authors: Philippe Galy, joao Quintino, Lorena Anghel, Yann Beilliard, Fabien Alibart, Dominique Drouin, Jury Sandrini, Franck Arnaud
Abstract: This study reports new preliminary results on pulse programmed 28 nm FD-SOI UTBB fully co-integrated phase change memories (PCM) at room (RT) and cryogenic temperatures (CT). The PCM is found to be functional at 77K featuring multi-state switching with no extra operating requirements compared to RT. As the phase change memory is temperature dependent, drift tests are carried out to track the resistance change overtime subsequent to pulse programming to estimate the drift coefficients. A striking feature is that using the same programming conditions, the drift coefficient is 3 times lower at 77K with improvement
Investigation on the Performance Limits of Dirac-Source FETs
Presenter: Tommaso Ugolini (University of Bologna)
Authors: Tommaso Ugolini, Elena Gnani
Abstract: The investigation in the area of steep-slope FETs was recently enriched by a proposal exploiting the conical band structure of graphene to control high-energy electron injection into the channel of a 2D-material based FET. In this work, we extend the approach adopted in Wu-Appenzeller by developing a two-dimensional (2D) simulation tool addressing Poisson’s equation within the MoS2 section of the DS-FET under the assumption of ballistic transport. Next, we compute the device characteristics, which are quite sensitive to the tunneling probability at the graphene-MoS2 heterojunction. Our results confirm that a subthreshold swing SS as low as 40 mV/dec can be achieved, and that SS values below 60 mV/dec are extended up to three and a half decades.
11:20 - 13:00
Session 5 learn more
Session 5
Operation of Junctionless Nanowire Transistors Down to 4.2 Kelvin
Presenter: Flavio Bergamaschi (CEA-Leti)
Authors: Flavio Bergamaschi, Jefferson Matos, Michelly de Souza, Sylvain Barraud, Mikaël Cassé, Olivier Faynot, Marcelo Pavanello
Abstract: In this work, an experimental analysis of the operation of junctionless nanowire transistors down to liquid helium temperatures is conducted. DC measurements are performed in a temperature range going from 300K down to 4.2K in devices with variable geometrical dimensions, namely the gate length and the fin width. Different electrical parameters are analyzed such as the threshold voltage, the subtrheshold slope, the low-field mobility and the drain-induced barrier lowering (DIBL).
Non-Uniform matching performances in mesa-isolated SOI MOSFETs
Presenter: Pierre Lheritier (CEA-LETI)
Authors: Pierre Lheritier, Giovanni Romano, Fabienne Ponthenier, Sylvain Joblot, Joris Lacord
Abstract: This work studies the threshold voltage mismatch of mesa-isolated SOI pMOSFETs through a breakdown between edge and center contributions. Pelgrom’s law is followed if a proper care is taken in the Vt extraction method. Applied to pMOS devices we observed that despite its parasitic nature, the edge transistor mismatch is as good as that of the center, regardless of channel doping. Even more, the edge mismatch appears to be less degraded when a positive bias is applied to the back-gate.
Analog Behavior of Forksheet at High Temperatures
Presenter: Joao Martino (USP)
Authors: Joao Martino, Paula Agopian, Julius Andretti, Romain Ritzenthaler, Hans Mertens, Anabela Veloso, Naoto Horiguchi
Abstract: This work presents the analog behavior of n-type forksheets from room to 150oC with channel lengths of 26 and 70 nm. These devices present a Zero Temperature-Coefficient (ZTC) point for gate voltage around 0,59 V (VZTC) in saturation region. The threshold voltage variation with temperature (dVT/dT) is around -0,5mV/oC due to the Fermi level decrease. The DIBL increase with temperature but it is kept lower than 51mV/V in the studied temperature range. The transconductance and output conductance decrease (mainly due the mobility degradation) which results in an intrinsic voltage gain around 36 dB, showing a slight change (±2dB) in the studied temperature range. The maximum unit gain frequency was estimated around 3.87 GHz in strong inversion regime. The results show that the forksheet can also be used for analog applications at high temperature, in addition to the already known savings in footprint area compared to nanosheet technology.
Investigation of DC and Low Frequency Noise Parameters of Junctionless GAA Si VNW pMOSFETs in the Temperature Range from 80 K to 340 K
Presenter: Abderrahim Tahiat (Normandie Univ, ENSICAEN, UNICAEN, CNRS, GREYC, Caen, 14000, France)
Authors: Abderrahim Tahiat, Bogdan Cretu , Anabela Veloso, Eddy Simoen
Abstract: In this article, junctionless vertical nanowire (JL VNW) Gate-all-around (GAA) silicon field-effect transistors (FETs) manufactured at imec, have been studied, by performing direct current (DC) and low-frequency noise (LFN) measurements in a wide range of temperature from 340 K down to 80 K. The aim of this experimental study is to investigate the temperature dependence of the extracted DC and LFN parameters and performance of the studied devices. The experimental DC results showed a decrease of the ION and a degradation of the low field mobility µ0 as the temperature decreases, the trend which we may attribute to the scattering by surface oxide charges. From the LFN measurements a correlation between the mobility degradation and the increasing of the estimated flat-band noise level Svfb when the temperature decreases is observed. A correlation was fond between mobility µ0 degradation and the estimated flat-band noise level (Svfb) and Nit increasing as exposed in figure 3.c. This correlation suggests an impact of the charge oxide traps on both 1/f noise level and low filed mobility through remote Coulomb scattering.
14:15 - 16:50
Session 6 learn more
Session 6

Brain-inspired In-memory Computing using Ferroelectric Transistors

Presenter: Hussam Amrouch

Novel Y-function methodology parameter estimation from weak to strong inversion operation
Presenter: Bogdan Cretu (Normandie Univ, ENSICAEN, UNICAEN, CNRS, GREYC, Caen, 14000, France)
Authors: Bogdan Cretu , Abderrahim Tahiat, Anabela Veloso, Eddy Simoen
Abstract: In this article a compact Y-function methodology is proposed, providing accurate and physical electrical parameters extraction and allowing to model the transfer characteristics behaviour from weak to strong inversion operation regime. The advantage of this new methodology is that no capacitance measurements or mathematical formulation as Lambert W function or Kubo-Greenwood modeling approach are necessary.
The Dual-Technology FET: nMOS/pTFET in the same device
Presenter: Joao Martino (University of Sao Paulo)
Authors: Carlos Augusto Bergfeld Mori, Pedro Henrique Duarte, Ricardo Cardoso Rangel, Paula Agopian, Joao Martino
Abstract: This work presents for the first time the experimental results of a Dual-Technology FET (DT-FET). DT-FET is a SOI transistor capable of operating either as an n-type MOSFET (nMOS) or a p-type Tunnel-FET (pTFET), depending on the back gate bias and the source/drain bias conditions. It is an extension of the BESOI MOSFET, with the addition of N+ at the drain or source region, which results in different physics of operation depending on back the gate bias. For a positive back gate bias the device behaves as an nMOS, while for a negative back gate bias it behaves as a pTFET. The results were compared with 2D simulations, showing that the overall trends are similar.
TLM-based numerical extraction for CMOS-compatible N+-InGaAs ohmic contacts on 200mm Si substrates
Presenter: Antoine Lombrez (Univ. Grenoble Alpes, CNRS, CEA/LETI-Minatec, Grenoble INP, LTM, Grenoble 38054 France)
Authors: Antoine Lombrez, Alexis Divay, Hervé Boutry, Léo Colas, Nicolas Coudurier, Stéphane Altazin, Thierry Baron
Abstract: Abstract – We report the results of a TLM-based numerical extraction methodology applied on CMOS-compatible n+-InGaAs ohmic contacts integrated with dielectrics on 200mm Si substrate. We obtained state-of-the-art level ρc = 7,5.10-8 ohm.cm² for relevant contact dimensions (THz HBT for 6G). This methodology is first described and calibrated using contacts on SOI. Conclusion – A TLM-based numerical extraction has been proposed to properly extract the sheet resistance and contact resistivity of CMOS-compatible ohmic contacts on n-InGaAs layers. This refinement allows to reduce errors by 15.3% compared to classical TLM extraction for such scaled contacts. The obtained ρc value is compatible with 6G THz applications and comparable to the state-of-the-art.
09:00 - 11:05
Session 7 learn more
Session 7

Spintronic logic gates and circuits

Presenter: Florin Ciubotaru

Effect of Al2O3 on the operation of SiNX-based MIS RRAMs
Presenter: Alexandros Mavropoulis (Institute of Nanoscience and Nanotechnology, NCSR “Demokritos”)
Authors: Alexandros Mavropoulis, Nikolaos Vasileiadis, Pascal Normand, Christoforos Theodorou, Georgios Ch. Sirakoulis, Sungjun Kim, Dimitrakis Panagiotis
Abstract: The effect of Al2O3 on the operation of SiNx-based MIS RRAMs is studied by utilizing various electrical characterization and impedance spectroscopy experiments. The main operation parameters of the fabricated devices are studied (SET/RESET voltage, operation cycles, dielectric constant) and they are compared with a reference sample with only SiNx as resistive switching material to reveal the role of Al2O3.
Amorphous TeO2 as P-type Oxide Semiconductor for Electronic Devices
Presenter: John Robertson (Cambridge University)
Authors: John Robertson
Abstract: Back-end-of-line devices need amorphous dopable bipolar ox-ide semiconductors. However, there are no practical p-type oxides, they are layered, require high processing temperatures or ineffective due to self-compensation by native defects. TeO2 is a glass. Our simulations find that amorphous (a-) TeO2 is chemically ordered, can be degenerately doped p-type, does not self-compensate and uses low-cost processable materials.
Trap Characterization in Substrates with Buried SiGe Layers for RF
Presenter: Yiyi Yan (Université catholique de Louvain)
Authors: Yiyi Yan, Martin Rack, Martin Vanbrabant, Massinissa Nabet, Andreas Goebel, Paul Clifton, Jean-Pierre Raskin
Abstract: In this work, the conductance method analyzes the interface trap density (Dit) between BOX and Silicon germanium (SiGe) on the SOI substrate. Both small signal measurements and simulations demonstrated that high Dit extracted at interface SiO2/SiGe can neutralize the free carriers coming from bulk, thus overcoming the parasitic surface conduction (PSC) effect and ensuring a state of high resistivity. High resistivity (HR) buried SiGe substrate emerges as a promising candidate for RF SOI integration.
Substrate Crosstalk Characterization for optimized Isolation in FDSOI
Presenter: Talha Chohan (GlobalFoundries Dresden, Germany)
Authors: Talha Chohan, Zhixing Zhao, Luca Pirro, Loren Dombroske, Jacob Ong, Olaf Zimmerhackl, Steffen Lehmann, David Pritchard, Tao Xue, Jan Hoentschel
Abstract: The continued large-scale integration of CMOS technologies has enabled complex system on chip applications. These systems often integrate a logic circuits (aggressor) along with sensitive analog and RF circuit blocks (victim). The dynamic signal switching of logic block couples through the substrate and impact the performance or functionality of the sensitive analog/RF block. The fundamentals of crosstalk between noise source and victim are well discussed in the literature. The approach for crosstalk reduction is often driven in terms of substrate resistivity (i.e., either very low (~1 mꭥ.cm) [1] or high (>1 kꭥ.cm)) and introduction of conductive layers in SOI system. It has been demonstrated that triple wells in bulk CMOS can be equal or better in isolation compared to SOI. However, for mixed mode CMOS circuits, the choice of specialized substrate is not trivial. This work consolidates the solutions of crosstalk reduction in commercial SOI resistivity substrate (~1 – 100 ꭥ.cm) by investigating design-based solutions in fully depleted SOI (FDSOI) technology. This crosstalk study evaluates the isolation in term of SOI vs. bulk, junction impact, lateral resistance, and noise shunting elements (guard-rings). A novel guard-ring scheme deploying the combination of resistive and capacitive elements for a superior isolation is demonstrated.
11:20 - 13:00
Session 8 learn more
Session 8
GaN-on-GaN PiN Diode Performance at Cryogenic Temperatures
Presenter: Ya-Xun Lin (Department of Electrical Engineering and Electronics, University of Liverpool)
Authors: Ya-Xun Lin, Der-Sheng Chao, Jenq-Horng Liang, Steve Hall, Jiafeng Zhou, Ivona Mitrovic
Abstract: 1. The performance of GaN on GaN PiN diodes are evaluated at cryogenic temperature. 2. The physical models need further optimization and improvement to facilitate the study of current transport at cryogenic temperature.
Low-frequency Noise in Polysilicon Source-Gated Thin-Film Transistor
Presenter: Qi Chen (ICTEAM, UCLouvain)
Authors: Qi Chen, Léopold Brandt, Valeriya Kilchytska, Radu Sporea, Denis Flandre
Abstract: The low-frequency noise (LFN) of SOI-based polysilicon Source-gated transistors (SGT) and thin-film field-effect transistor (TFET) is investigated. It appears that the LFN of SGT is dominated by carrier number fluctuation (CNF) in high Id region and by Schottky barrier height fluctuation in low Id region. The low-frequency noise of polysilicon TFET appears mainly correlated with the carrier mobility fluctuation (CMF), while CNF is not completely ruled out.
DFT study of adsorption density of gas molecules in 2D materials
Presenter: Ruben Ortega Lopez (CITIC, University of Granada)
Authors: Ruben Ortega Lopez, Luca Donetti, Carlos Navarro Moral, Carlos Marquez Gonzalez, Francisco Gamiz Perez
Abstract: A DFT study of gas molecules adsorption in 2D materials has been presented with applications in gas sensing. As an application, the density of adsorption of NH3 and N2 has been computed for monolayer MoS2 as sensing material.
Performance of Pulse-Programmed Memristive Crossbar Array with Bimodally Distributed Stochastic Synaptic Weights
Presenter: Nadine Dersch (NanoP, THM University of Applied Sciences, Giessen, Germany and DEEEA, Universitat Rovira i Virgili, Tarragona, Spain)
Authors: Nadine Dersch, Eduardo Perez, Christian Wenger, Christian Roemer, Mike Schwarz, Benjamin Iniguez, Alexander Kloes
Abstract: In this paper, we present a method of implementing memristive crossbar array with bimodally distributed weights. The bimodal distribution is a result of pulse-based programming. The memristive devices are used for the weights and can only have an ON (logical "1") or an OFF (logical "0") state. The state of the memristive device after programming is determined by the bimodal distribution. The highly efficient noise-based variability approach is used to simulate this stochasticity. The memristive crossbar array is used to classify the MNIST data set and comprises more than 15,000 weights. The interpretation of these weights is investigated. In addition, the influence of the stochasticity of the weights and the accuracy of the weights on the classification results is considered.
Interface Roughness in Resonant Tunnelling Diodes for Physically Unclonable Functions
Presenter: Pranav Acharya (University of Glasgow)
Authors: Pranav Acharya, Vihar Georgiev
Abstract: Resonant Tunnelling Diodes (RTDs) with Interface Roughness (IR) between the AlGaAs barriers and GaAs body and quantum well (QW) were simulated using Nano-electronic Simulation Software (NESS). This used Non-equilibrium’s Green’s Function (NEGF) solver to capture quantum tunnelling behaviour. 25 devices were randomly generated and simulated for different correlation length and root-mean-square roughness asperity. It was found that a correlation length of 7.5nm and asperity of 0.3nm balance Peak to Valley Current Ratio (PVCR) voltage and current standard deviations, for the purpose of using RTDs as a Physically Unclonable Functions (PUF) component, hence this was visualised. This research provides a direction for further research of RTDs as a PUF component.
14:15 - 17:10
Session 9 learn more
Session 9
Influence of multiple MISHEMT conduction channels on analog behavior
Presenter: Bruno Canales (LSI/PSI/USP, University of Sao Paulo, Sao Paulo, Brazil)
Authors: Bruno Canales, Bruno Sanches, Joao Martino, Eddy Simoen, Uthayasankaran Peralagu, Bertrand Parvais, Nadine Collaert, Paula Agopian
Abstract: In this paper, the multiple channels of a MISHEMT device (Metal/Si3N4/AlGaN/AlN/GaN - Metal-Insulator-Semiconductor High Electron Mobility Transistor) are studied regarding their impact on basic DC and RF figures of merit. Although most authors treat the 2DEG channel as the MISHEMT main channel, it is shown that its MOS channel contribution to the different RF parameters is of great importance. This unique characteristic makes the MISHEMT RF parameters to be dependent on both VGS and VDS. In relation to a pure 2DEG conduction, the MOS channel is responsible for a large set of analog parameters improvements. It offers an increase of up to 17.6 dB in S21 and of 23 dB in MAG, while sustaining a high fT and fmax for a larger range of VGS and drain current level.
Optimizing Unconventional Trilayer SOTs for Field-Free Switching
Presenter: Nils Petter Jørstad (Institute for Microelectronics, TU Wien)
Authors: Nils Petter Jørstad, Wolfgang Goes, Siegfried Selberherr, Viktor Sverdlov
Abstract: We demonstrate that FePt/Cu/CoFeB trilayers can generate unconventional SOTs acting on the CoFeB layer, tunable by the FePt magnetization direction. Our spin drift-diffusion approach enables the study and optimization of SOTs concerning materials, layer thickness, and magnetization directions. Ultimately, coupling the computed torques with the Landau-Lifshitz-Gilbert equation is essential for investigating the resulting magnetization dynamics in order to demonstrate deterministic field-free switching.
Electron mobility in silicon under high uniaxial strain
Presenter: Nicolas Roisin (UCLouvain)
Authors: Nicolas Roisin, Loïc Lahaye, Jean-Pierre Raskin, Denis Flandre
Abstract: In the pursuit of enhancing the performance of semiconductor devices, the manipulation of material properties through strain engineering has emerged as a promising avenue. The enhancement of the electron mobility in silicon has been experimentally investigated for uniaxial strain up to 1% applied along the [100] crystal direction. A significant improvement in the mobility has been observed at high strain, which was underestimated in previous theoretical studies. The measurements have also been validated with theoretical analysis, which extends beyond the existing models based solely on the splitting of valley energies due to strain.
Towards ALD-grown MoS2 devices for CMOS BEOL
Presenter: Carlos Marquez Gonzalez (CITIC, University of Granada)
Authors: Francisco Lorenzo, Jose Carlos Galdon, Ruben Ortega Lopez, Manuel Caño-Garcia, Luca Donetti, Carlos Navarro Moral, Francisco Gamiz Perez
Abstract: The achievement of isolated graphene in 2004 by Geim and Novoselov has significantly boosted research in two-dimensional (2D) materials. Among the most promising 2D materials for the next electronic nodes are the transition metal dichalcogenides (TMDs), which present: i) suitable bandgaps to be compatible with CMOS technology, ii) large effective masses reducing source-to-drain tunneling, iii) controllable thicknesses at the atomic level allowing excellent electrostatic control. However, difficulties in their fabrication such as the scarcity of scalable fabrication methods still suppose a bottleneck for their industrial implantation. We present MoS2 back-gated devices synthesized via ALD at temperature compatible with CMOS. Raman, AFM and electrical characterization have been performed to optimize the fabrication parameters.
Back Bias Effect with Hysteresis in Cryogenic 200 nm SOI MOSFETs
Presenter: Ryusei Ri (Kanazawa Institute of Technology)
Authors: Ryusei Ri, Takayuki MORI, Hiroshi OKA, Takahiro MORI, Jiro IDA
Abstract: We report the novel finding of the hysteresis effect, which only occurs at cryogenic temperatures, observed when the substrate voltage is continuously applied to a 200nm SOI MOSFET. We suggest that the hysteresis is due to carrier trapping and depletion on the box side, which occurs when the backside channel of the device is turned on.
Interlayer Exchange Coupling for Enhanced Performance in Spin-Transfer Torque MRAM Devices
Presenter: Mario Bendra (TU Vienna)
Authors: Mario Bendra, Johannes Ender, Roberto L. de Orio, Siegfried Selberherr, Wolfgang Goes, Viktor Sverdlov
Abstract: This research delves into the optimization of Magnetic Tunnel Junctions (MTJs) in Spin-transfer torque magnetoresistive random access memory (STT-MRAM), focusing on the role of Interlayer Exchange Coupling (IEC) in enhancing device performance and reliability. By examining the magnetic alignment within MTJs, particularly in CoFeB-based structures, the study addresses miniaturization challenges such as back-hopping. Utilizing the Landau-Lifshitz-Gilbert (LLG) equation, the research explores magnetization dynamics and the influence of IEC on magnetic switching processes. Initial simulations suggest that tuning the IEC can significantly improve switching speeds, data retention, and overall device reliability. This investigation highlights the intricate impact of magnetic coupling in STT-MRAM devices and proposes a path forward in memory technology optimization through precise engineering of IEC.
Quantum Simulations of MoS2 FETs Including Contact Effects
Presenter: Alfonso Sanchez-Soares (EOLAS Designs)
Authors: Alfonso Sanchez-Soares, Thomas Kelly, Sheng-Kai Su, Edward Chen, James Greer, Giorgos Fagas
Abstract: 2D materials have attracted considerable interest for applications in field-effect transistors (FETs) given their potential for high packing densities and excellent electrostatic control. However, achieving low contact resistances remains one of main fabrication challenges. This study presents a methodology that enables device simulations explicitly including the effects of contact interfaces within a quantum mechanical framework. We demonstrate its potential for device and contact engineering by validating our approach against experimental and ab-initio simulation results for Bi contacts in MoS2-based devices.
Density Functional Analysis of Voltage Shifts through Oxide Layers in Si- and MoS2-based FETs
Presenter: Ruyue Cao (University of Cambridge)
Authors: Ruyue Cao, zhaofu zhang, Yuzheng Guo, John Robertson
Abstract: We analyze voltage shifts of oxide layers like SrO, La2O3, HfO2, and Al2O3 used to set threshold voltages (Vth) in high-K/metal CMOS gate stacks by density functional theory. They are due to a combination of dipole effects and band alignments. This allows such layers to adjust the electrode Fermi levels (EF) in either n-type or p-type directions. These methods are extended to 2D TMD-channel transistors, such as MoS2. Here, MoS2 inevitably contains sulfur vacancies, making it n-type. We show here that adding an Al2O3 layer to the high-K layers will shift EF downwards to regain mid-gap behavior. This allows us to achieve true inversion mode MoS2 FETs.